| Main objective |
The major goal of this project is to design, integrate in a 90nm CMOS technology and experimentally evaluate a calibration-free 2-channel time-interleaved 6-bit 1GS/s CMOS Pipeline ADC with an EE better than 0.2-0.3 pJ per conversion step and at the same time achieving a very low die area. Many novel techniques will be addressed to reach such goal such as, intensive use of passive structures, amplifier sharing, simple amplifier topology and exhaustive circuit optimization. A second aim of the project will be to include, on-chip, an efficient solution for providing built-in self-testing capability.
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