Academic position:
Post. Doc.
Joining date:
14-05-2012
Role in IT: Researcher Scientific Area: Basic Sciences and Enabling Technologies
Group: Integrated Circuits – Av
Degrees
- PhD, Universidade de Aveiro, 01-01-2012 - MSc, Universidade de Aveiro, 01-01-2003 - Licenciatura, Universidade de Coimbra, 01-01-1999
Expertise Topics
- Digital Integrated Circuits - Circuits and Systems for Communications - Noise and Variability in Integrated Circuits
Affiliations
- Escola Superior de Tecnologia e Gestão - IPLEIRIA, Docente, 01-10-1999
Academic Activities
Lecture courses
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Sistemas Eletrónicos, Instituto Politécnico de Leiria, Mestrado em Eng. Eletrotécnica
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Projecto de Sistemas Electrónicos, Instituto Politécnico de Leiria, Engenharia Electrotécnica - Ramo de Electrónica e Telecomunicaçoes
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Sistemas Digitais, Instituto Politécnico de Leiria, Engenharia Electrotécnica
Supervision of theses
Undergraduate
- Pico Robot, Undergraduate, Dinis Belo e Sérgio Silva, 7-2013, Instituto Politécnico de Leiria
- RF Localization System, Undergraduate, João Neto, 7-2013, Instituto Politécnico de Leiria
Co - Supervision of Theses
Undergraduate
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RF Detection and Localisation System - ver2, Undergraduate, João Paulo Gomes Neto, 7-2013
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RF Location and detection system, Undergraduate, Marco Roda and Tiago Silva , 7-2012
Publications
Papers in Journals [3]
- Figueiredo, M.; Aguiar, R. L.; "A Jitter Insertion and Accumulation Model for Clock Repeaters", IEICE Trans. on Electronics, Vol. Vol.E95-A, No. No.12, pp. 2430 - 2442, December, 2012.
| BibTex
- Figueiredo, M.; Aguiar, R. L.; "A Dynamic Jitter Model to Evaluate Uncertainty Trends with Technology Scaling", Integration, The VLSI Journal, Vol. 45, No. 2, pp. 162 - 171, March, 2012. Abstract
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Design and Perfomance of 155Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs", Analog Integrated Circuits and Signal Processing, Vol. 43, No. 0, pp. 0 - 0, May, 2005.
| BibTex
Papers in Conference Proceedings [14]
- Figueiredo, M.; Aguiar, R. L.; "Uncertainty in DLL Deskewing Schemes", Proc IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Seville, Spain, Vol. n.a., pp. 841 - 844, December, 2012.
| BibTex
- Figueiredo, M.; Aguiar, R. L.; "Dynamic Jitter Accumulation in Clock Repeaters Considering Power and Ground Noise Correlations", Proc IEEE International Symp. on Circuits and Systems - ISCAS, Rio de Janeiro, Brazil, Vol. n.a., pp. n.a. - n.a., May, 2011.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis", Proc International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS, Delft, Netherlands, Vol. 0, pp. 0 - 0, September, 2009.
| BibTex
- Figueiredo, M.; Aguiar, R. L.; "Time Precision Comparison of Digitally Controlled Delay Elements", Proc IEEE International Symp. on Circuits and Systems - ISCAS, Taipei, Taiwan, Vol. --, pp. -- - --, May, 2009.
Abstract
| BibTex
- J. P. Pinhal; B. D. Dias; Figueiredo, M.; "Desempenho de TDCs para Medição de Jitter em FPGAs de Baixo Custo ", Proc Jornadas de Engenharia de Electrónica e Telecomunicações e de Computadores do ISEL, Lisboa, Portugal, Vol. --, pp. -- - --, November, 2008.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "A Study on CMOS Time Uncertainty with Technology Scaling", Proc International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS, Lisbon, Portugal, Vol. 0, pp. 0 - 0, September, 2008.
Abstract
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Predicting Noise and Jitter in CMOS Inverters", Proc IEEE PhD. Research in Microelectronics and Electronics - PRIME, Bordeaux, France, Vol. 0, pp. 0 - 0, July, 2007.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Noise Induced Jitter Performance of Digitally Controlled CMOS Delay Lines", Proc Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol. 0, pp. 0 - 0, May, 2007.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Noise and Jitter in CMOS Digitally Controlled Delay Lines", Proc IEEE Conf. on Electronics, Circuits and System, Nice, France, Vol. 0, pp. 0 - 0, December, 2006.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Performance of 155Mbps Clock/data Recovery Circuits on Heavy Loaded PLDs", Proc IEEE Conf. on Electronics, Circuits and System, Sharjan, United Arab Emirates, Vol. 1, pp. 1 - 1, December, 2003.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Resource Constrained 155Mbps Clock and Data Recovery with 4x Oversampling and Jitter Reduction", Proc Conf. on Design of Circuits and Integrated Systems, Malaga, Spain, Vol. 1, pp. 1 - 1, November, 2002.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Resource Constrained Clock Recovery on Programmable Logic Devices", Proc IEEE International Conf. on Electronics, Circuits and Systems, Dubrovnik, Croatia, Vol. 1, pp. 1 - 1, September, 2002.
| BibTex
- Aguiar, R. L.; Figueiredo, M.; "Métodos de Recuperação de Relógio em Dispositivos de Lógica Programável", Proc Conf. Científica e Tecnológica em Engenharia - CCTE, Lisboa, Portugal, Vol. 1, pp. 1 - 1, May, 2002.
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